Thin film transistor array panel and method for manufacturing the same

ABSTRACT

A thin film transistor array panel includes a substrate; a first gate line disposed on the substrate and including a gate electrode; a storage electrode disposed in a layer which is the same layer as a layer of the first gate line; a gate insulating layer disposed on the first gate line and the storage electrode; a semiconductor disposed on the gate insulating layer and including a channel portion; a data line disposed on the semiconductor and including a source electrode; a drain electrode disposed on the semiconductor and facing the source electrode; a passivation layer disposed on the gate insulating layer, the data line, and the drain electrode, the passivation layer including a contact hole which exposes a portion of the drain electrode; and a pixel electrode disposed on the passivation layer and electrically connected to the drain electrode through the contact hole, wherein the gate insulating layer and the passivation layer are interposed between the pixel electrode and the substrate except for a region corresponding to the contact hole, and wherein the pixel electrode overlaps the storage electrode via the gate insulating layer and the passivation layer.

This application is a divisional of U.S. application Ser. No.12/354,130, filed on Jan. 15, 2009, which claims priority to KoreanPatent Application No. 10-2008-0087372, filed on Sep. 4, 2008, and allthe benefits accruing therefrom under 35 U.S.C. §119, the contents ofwhich in its entirety are herein incorporated by reference.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

This disclosure relates to a thin film transistor array panel and amethod for manufacturing the same.

(b) Description of the Related Art

A thin film transistor is used as a switching element to independentlydrive each pixel in a flat panel display device, such as a liquidcrystal display or an organic light-emitting device. The thin filmtransistor array panel includes a thin film transistor, a scanningsignal line (or a gate line) for transmitting a scanning signal to thethin film transistor, and a data line for transmitting a data signal, aswell as a pixel electrode electrically connected to the thin filmtransistor.

To form a thin film transistor array panel, several photolithographicprocesses are required, and each photolithographic process can includeseveral tens to several hundreds of steps, thus if the number ofphotolithographic processes is increased, a process time and a cost areincreased. Accordingly, various methods to reduce the number ofphotolithographic processes have been proposed, however there areproblems involved with reducing the number of photolithographicprocesses such that it is difficult to reduce the number thereof.

BRIEF SUMMARY OF THE INVENTION

The above described and other drawbacks are alleviated by a thin filmtransistor array panel including a substrate; a first gate line disposedon the substrate and including a gate electrode; a storage electrodedisposed in a layer which is the same layer as a layer of the first gateline; a gate insulating layer disposed on the first gate line and thestorage electrode; a semiconductor disposed on the gate insulating layerand including a channel portion; a data line disposed on thesemiconductor and including a source electrode; a drain electrodedisposed on the semiconductor and facing the source electrode; apassivation layer disposed on the gate insulating layer, the data line,and the drain electrode, the passivation layer including a contact holewhich exposes a portion of the drain electrode; and a pixel electrodedisposed on the passivation layer and electrically connected to thedrain electrode through the contact hole, wherein the gate insulatinglayer and the passivation layer are interposed between the pixelelectrode and the substrate except for a region corresponding to thecontact hole, and wherein the pixel electrode overlaps the storageelectrode via the gate insulating layer and the passivation layer.

In an embodiment, the storage electrode may include a portion of asecond gate line, which is parallel to the first gate line, andtransmits a gate signal.

In an embodiment, the passivation layer may further include a firstopening which exposes an end portion of the first gate line, and asecond opening, which exposes an end portion of the data line, andwherein the thin film transistor array may further include a firstcontact assistant disposed in the first opening and electricallyconnected to the end portion of the first gate line; and a secondcontact assistant disposed in the second opening and electricallyconnected to the end portion of the data line.

In an embodiment, the first contact assistant may further contact thesubstrate surrounding the end portion of the first gate line, and thesecond contact assistant may further contact the substrate surroundingthe end portion of the data line.

In an embodiment, a planar shape of the semiconductor, except for thechannel portion, may be the same as a planar shape of the data line andthe drain electrode.

In an embodiment, the storage electrode may include a portion of asecond gate line, which is parallel to the first gate line and transmitsa gate signal.

In an embodiment, the passivation layer may further include a firstopening, which exposes an end portion of the first gate line, and asecond opening, which exposes an end portion of the data line, andwherein the thin film transistor array panel may further include a firstcontact assistant disposed in the first opening and electricallyconnected to the end portion of the first gate line; and a secondcontact assistant disposed in the second opening and electricallyconnected to the end portion of the data line.

In an embodiment, the first contact assistant may further contact thesubstrate surrounding the end portion of the first gate line, and thesecond contact assistant may further contact the substrate surroundingthe end portion of the data line.

In an embodiment, a manufacturing method of a thin film transistor arraypanel includes disposing a first gate line including a gate electrodeand an end portion on a substrate; disposing a gate insulating layer onthe first gate line; disposing a semiconductor including a channelportion, a data line including a source electrode and an end portion,and a drain electrode on the gate insulating layer; disposing apassivation layer on the gate insulating layer, the data line, the drainelectrode, and the channel portion of the semiconductor; disposing aphotosensitive film on the passivation layer and exposing thephotosensitive film to light using a first photo mask to form a firstphotosensitive film pattern, which includes a first portion and a secondportion, the second portion having a thickness which is greater than athickness of the first portion, the first photosensitive film patternexposing a portion of the passivation layer on a portion of the drainelectrode; removing the exposed portion of the passivation layer usingthe first photosensitive film pattern as a mask; etching the firstphotosensitive film pattern to remove the first portion to form a secondphotosensitive film pattern; disposing a conductive layer on the secondphotosensitive film pattern; heating the second photosensitive filmpattern to form cracks in the conductive layer; and forming a pixelelectrode by removing the second photosensitive film pattern, the pixelelectrode contacting a portion of the drain electrode and disposed on aportion of the passivation layer exposed by the removal of the firstportion of the first photosensitive film pattern.

In an embodiment, the first photo mask may include a first transparentregion through which where light is transmitted, a first opaque regionwhere light is blocked, and a first translucent region which correspondsto the first portion and through which light is partially transmitted.

In an embodiment, the first translucent region may include at least oneof a slit, a lattice pattern, and a translucent film.

In an embodiment, disposing the semiconductor, the data line, and thedrain electrode may further include disposing a second photo mask.

In an embodiment, disposing the semiconductor, and the data line and thedrain electrode may include disposing sequentially an intrinsicsemiconductor layer, an impurity-doped semiconductor layer, and a dataconductive layer on the gate insulating layer; disposing aphotosensitive film on the data conductive layer and exposing thephotosensitive film to light using the second photo mask to form a thirdphotosensitive film pattern, which includes a third portioncorresponding to the channel portion of the semiconductor, and a fourthportion, the fourth portion including a thickness which is greater thana thickness of the third portion; removing a portion of the dataconductive layer, a portion of the impurity-doped semiconductor layer,and a portion of the semiconductor layer using the third photosensitivefilm pattern as a mask; etching the third photosensitive film pattern toremove the third portion to form a fourth photosensitive film pattern;and etching the data conductive layer and the impurity-dopedsemiconductor layer exposed by the removal of the third portion usingthe fourth photosensitive film pattern as a mask.

In an embodiment, the second photo mask may further include a secondtransparent region through which light is transmitted, a second opaqueregion where light is blocked, and a second translucent region throughwhich light is partially transmitted.

In an embodiment, the first photosensitive film pattern may furtherexpose a portion of the passivation layer disposed on the end portion ofthe first gate line and a portion of passivation layer disposed on theend portion of the data line, and the forming of the pixel electrode mayfurther include disposing first and second contact assistantsrespectively contacting the end portion of the first gate line and theend portion of the data line.

In an embodiment, removing the portion of the passivation layer mayfurther include etching the gate insulating layer using the firstphotosensitive film pattern as a mask to expose the end portion of thefirst gate line.

In an embodiment, etching the gate insulating layer further includesexposing the substrate surrounding the end portion of the first gateline and the substrate surrounding the end portion of the data line.

In an embodiment, disposing the semiconductor, the data line, and thedrain electrode may further include disposing a second photo mask.

In an embodiment, the disposing of the first gate line further includesdisposing a second gate line overlapping the pixel electrode via thegate insulating layer and the passivation layer.

In an embodiment, the disposing of the first gate line further includesdisposing a storage electrode overlapping the pixel electrode via thegate insulating layer and the passivation layer.

In an embodiment, the heating may be at a temperature between about 100°C. to about 250° C.

These and other features, aspects, and advantages of the disclosedembodiments will become better understood with reference to thefollowing description and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, advantages, and features of the inventionwill become more apparent by describing in further detail exemplaryembodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a plan view showing an exemplary embodiment of signal linesand pixel electrodes in a thin film transistor array panel;

FIG. 2 is a plan view showing an exemplary embodiment of a thin filmtransistor array panel;

FIG. 3A is a cross-sectional view showing an exemplary embodiment of thethin film transistor array panel shown in FIG. 2 taken along lineIIIA-IIIA′;

FIG. 3B is a cross-sectional view showing an exemplary embodiment of thethin film transistor array panel shown in FIG. 1 taken along linesIIIB-IIIB′ and IIIB′-IIIB″;

FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG.11A, FIG. 12A, FIG. 13A, and FIG. 14A are cross-sectional views showingan exemplary embodiment of intermediate parts of a manufacturing processof the thin film transistor array panel shown in FIG. 2 taken along lineIIIA-IIIA′; and

FIG. 4B, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG.11B, FIG. 12B, FIG. 13B and FIG. 14B are cross-sectional views showingan exemplary embodiment of intermediate parts of a manufacturing processof the thin film transistor array panel shown in FIG. 2 taken alonglines IIIB-IIIB′ and IIIB′-IIIB″.

The detailed description explains the disclosed embodiments, togetherwith advantages and features, by way of example with reference to thedrawings.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. As those skilled in the art would realize,the described embodiments may be modified in various different ways, allwithout departing from the spirit or scope of the present invention.Thus aspects, advantages, and features of the present invention andmethods of accomplishing the same may be understood more readily byreference to the following detailed description of preferred embodimentsand the accompanying drawings. The present invention may, however, maybe embodied in many different forms, and should not be construed asbeing limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete and will fully convey the concept of the invention to thoseskilled in the art, and the present invention will only be defined bythe appended claims. Like reference numerals refer to like elementsthroughout the specification.

In the drawings, the thickness of layers, films, panels, regions, etc.,are exaggerated for clarity. Like reference numerals designate likeelements throughout the specification. It will be understood that whenan element such as a layer, film, region, or substrate is referred to asbeing “on” another element, it can be directly on the other element orintervening elements may also be present. In contrast, when an elementis referred to as being “directly on” another element, there are nointervening elements present.

As used herein, the term “and/or” includes any and all combinations ofone or more of the associated listed items.

It will be understood that, although the terms first, second, third,etc., may be used herein to describe various elements, components,regions, layers and/or sections, these elements, components, regions,layers and/or sections should not be limited by these terms. These termsare only used to distinguish one element, component, region, layer, orsection from another region, layer, or section. Thus, a first element,component, region, layer, or section discussed below could be termed asecond element, component, region, layer, or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “below”, “lower”, “upper” and thelike, may be used herein for ease of description to describe one elementor feature's relationship to another element(s) or feature(s) asillustrated in the figures. It will be understood that the spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as “below” or “lower” relative to other elements orfeatures would then be oriented “above” relative to the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing.

For example, an implanted region illustrated as a rectangle will,typically, have rounded or curved features and/or a gradient of implantconcentration at its edges rather than a binary change from implanted tonon-implanted region. Likewise, a buried region formed by implantationmay result in some implantation in the region between the buried regionand the surface through which the implantation takes place. Thus, theregions illustrated in the figures are schematic in nature and theirshapes are not intended to illustrate the actual shape of a region of adevice and are not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

All methods described herein can be performed in a suitable order unlessotherwise indicated herein or otherwise clearly contradicted by context.The use of any and all examples, or exemplary language (e.g., “suchas”), is intended merely to better illustrate the invention and does notpose a limitation on the scope of the invention unless otherwiseclaimed. No language in the specification should be construed asindicating any non-claimed element as essential to the practice of theinvention as used herein.

Hereinafter, the present invention will be described in detail withreference to the accompanying drawings. However, the aspects, features,and advantages of the present invention are not restricted to the onesset forth herein. The above and other aspects, features, and advantagesof the present invention will become more apparent to one of ordinaryskill in the art to which the present invention pertains by referencinga detailed description of the present invention given below.

A thin film transistor array panel according to an exemplary embodimentis described in detail with reference to FIG. 1.

FIG. 1 is a plan view showing an exemplary embodiment of signal linesand pixel electrodes in a thin film transistor array panel.

Referring to FIG. 1, a thin film transistor array panel according to anexemplary embodiment includes a plurality of gate lines 121, (i=1, n−1,n, n+1, etc.), a plurality of data lines 171 (j=1, m, m+1, etc.), and aplurality of pixel electrodes (191 _(i,j)) (i=1, n, n+1, etc.) (j=1, m,m+1, etc.) electrically connected thereto and substantially arranged ina matrix.

The gate lines 121 _(i) (i=1, n−1, n, n+1, etc.) extend substantially ina row direction and include a plurality of longitudinal lines andtransverse lines connected to the longitudinal lines at lower portionsof the longitudinal lines, the transverse lines extending in the rowdirection. The gate lines 121 _(i) (i=1, n−1, n, n+1, etc.) transmit agate signal comprising a combination of a gate-on voltage (“Von”) forturning on a switching element (not shown) and a gate-off voltage(“Voff”) for turning off the switching element.

The data lines 171 _(j) (j=1, m, m+1, etc.) transmit a data signal andextend substantially in a column direction.

The pixel electrode (191 _(i,j)) (i=1, n, n+1, etc.) (j=1, m, m+1, etc.)of the i^(th) row and j^(th) column is electrically connected to thei^(th) (i=1, n−1, n, n+1, etc.) gate line 121 _(i) and the j^(th) (j=1,m, m+1, etc.) data line 171 _(j) through a respective switching element(not shown).

The gate-on voltage Von is sequentially applied to the gate lines 121_(i) (i=1, n−1, n, n+1, etc.) to sequentially turn on switching elements(not shown), which are electrically connected to the gate lines 121 _(i)(i=1, n−1, n, n+1, etc.) such that data voltages applied to the datalines 171 _(j) (j=1, m, m+1, etc.) are transmitted to the pixelelectrodes (191 _(i,j)) (i=1, n, n+1, etc.) (j=1, m, m+1, etc.) throughthe switching elements (not shown), which are turned on.

Each pixel electrode (191 _(i,j)) (i=1, n, n+1, etc.) (j=1, m, m+1,etc.) may maintain the applied data voltage by overlapping the previousgate line (121 _(i−1), i=2, n, n+1, etc.) via an insulating layer. Forexample, the pixel electrode 191 _(n,j) (j=1, m, m+1, etc.) disposed inthe n^(th) row overlaps the previous gate line, which is the (n−1)^(th)gate line 121 _(n−1).

A thin film transistor array panel according to an exemplary embodimentwill be described in detail with reference to FIG. 2 to FIG. 3B.

FIG. 2 is a plan view showing an exemplary embodiment of a thin filmtransistor array panel, FIG. 3A is a cross-sectional view showing anexemplary embodiment of the thin film transistor array panel shown inFIG. 2 taken along line IIIA-IIIA′, and FIG. 3B is a cross-sectionalview showing an exemplary embodiment of the thin film transistor arraypanel shown in FIG. 1 taken along lines IIIB-IIIB′ and IIIB′-IIIB″.

A plurality of gate lines 121 are disposed on an insulating substrate110 and may comprise transparent glass, transparent plastic, or thelike, or a combination comprising at least one of the foregoingmaterials. Each gate line 121 transmits a gate signal and extends in therow direction, and includes a plurality of gate electrodes 124 extendingin a downward direction, and a gate line end portion 129 for electricalconnection with another layer or a gate driver (not shown). Also, eachgate line 121 includes a plurality of longitudinal portions 125 and atransverse portion 126 connected to lower portions of the longitudinalportions 125, the transverse portions extending in a row direction.

The gate lines 121 may comprise a metal having a low resistance, such asan aluminum-based metal. The gate lines 121 may comprise aluminum (Al),an aluminum alloy, a silver-based metal, silver (Ag), a silver alloy, acopper-based metal of copper (Cu), a copper alloy, or the like, or acombination comprising at least one of the foregoing metals.

A gate insulating layer 140 may comprise silicon nitride (SiN_(x)),silicon oxide (SiO_(x)), or the like, or a combination comprising atleast one of the foregoing materials, and can be disposed on the gatelines 121.

A plurality of semiconductor stripes (not shown) may comprisehydrogenated amorphous silicon (“a-Si”), a polysilicon, or the like, ora combination comprising at least one of the foregoing materials, andare disposed on the gate insulating layer 140. The semiconductor stripes(not shown) extend substantially in a longitudinal direction, and thesemiconductor stripes (not shown) include a plurality of semiconductorstripe protrusions 154 extending therefrom toward the gate electrodes124, and an end portion of the semiconductor stripes. Each of thesemiconductor stripe protrusions 154 also includes a semiconductorquadrangle expansion 157.

A plurality of ohmic contact stripes (not shown) and ohmic contactislands 165 are disposed on the semiconductor stripe protrusions 154,semiconductor quadrangle expansions 157, and semiconductor end portion159. Each of the ohmic contact stripes (not shown) includes a pluralityof protrusions 163 extending according to the semiconductor stripeprotrusions 154, and an ohmic contact end portion 169, wherein the ohmiccontact stripe protrusions 163, and the ohmic contact islands 165 aredisposed on the semiconductor stripe protrusions 154 opposing each otherthereby forming a pair with respect to the gate electrode 124. Each ofthe ohmic contact stripe protrusions 163 includes an ohmic contactquadrangle expansion 167. The ohmic contact stripe protrusions 163,ohmic contact islands 165, ohmic contact quadrangle expansions 167, andohmic contact end portion 169 may comprise n+ hydrogenated amorphoussilicon in which an n-type impurity, such as phosphorus, is doped at ahigh concentration, a silicide, or the like, or a combination comprisingat least one of the foregoing materials.

A plurality of data lines 171 and a plurality of drain electrodes 175are disposed on the ohmic contact stripes (not shown) including theohmic contact stripe protrusions 163, ohmic contact islands 165, ohmiccontact quadrangle expansions 167, and ohmic contact end portion 169.

The data lines 171 transmit data voltages, and extend in a longitudinaldirection perpendicular to the gate lines 121. Each of the data lines171 includes a plurality of source electrodes 173 curved toward the gateelectrodes 124, and an end portion of the data line 179 for connectingto another layer or a data driver (not shown).

The drain electrodes 175 are disposed opposite to the source electrodes173, and each includes a drain electrode quadrangle end portion 177having a wide area and a bar-shaped end portion. The drain electrodequadrangle end portions 177 overlap the transverse portions 126 of thegate lines 121, and the bar-shaped end portions are each enclosed by acurved portion of each of the source electrodes 173.

A gate electrode 124, a source electrode 173, and a drain electrode 175form a thin film transistor (“TFT”) along with a semiconductor stripeprotrusion 154, and the channel of the thin film transistor is disposedin the semiconductor stripe protrusion 154 between the source electrode173 and the drain electrode 175.

The semiconductor stripe protrusions 154 include exposed portionsbetween the source electrodes 173 and the drain electrodes 175 which arenot covered by the ohmic contact stripes (not shown) including the ohmiccontact stiripe protrusions 163, the ohmic contact islands 165, theohmic contact quadrangle expansions 167, the ohmic contact end portions169, the data lines 171, and the drain electrodes 175. In an embodiment,the semiconductor stripe protrusions 154, the semiconductor quadrangleexpansions 157, and the semiconductor end portions 159, except for thesemiconductor stripe protrusions 154 where the thin film transistors aredisposed, comprise a planar shape which is the same as a planar shape ofthe data lines 171, the drain electrodes 175, and the underlying ohmiccontact stripe protrusions 163, ohmic contact islands 165, ohmic contactquadrangle expansions 167, and ohmic contact end portions 169. Also, theohmic contact stripe protrusions 163, ohmic contact islands 165, ohmiccontact quadrangle expansions 167, and ohmic contact end portions 169have a planar shape which is substantially the same as a planar shape ofthe data lines 171 and the drain electrodes 175.

A passivation layer 180 is disposed on the gate insulating layer 140,the data lines 171, the drain electrodes 175, and exposed portions ofthe semiconductor stripe protrusions 154. The passivation layer 180 maycomprise an inorganic insulator, such as silicon nitride or siliconoxide, an organic insulator, such as a resin, or the like, or acombination comprising at least one of the foregoing insulators, and mayhave a flat surface. The organic insulator may have a dielectricconstant of equal to or less than 6, specifically equal to or less than4, more specifically equal to or less than 3, and may be photosensitive.

The passivation layer 180 has a plurality of contact holes 185 exposingthe drain electrode quadrangle end portions 177 of the drain electrodes175, and the passivation layer 180 and the gate insulating layer 140have a plurality of first and second openings 181 and 182 respectivelyexposing the gate line end portions 129 of the gate lines 121 and thedate line end portions 179 the data lines 171. The first and secondopenings 181 and 182 may further expose the substrate 110 surroundingthe gate line end portions 129 and data line end portions 179 of thegate lines 121 and the data lines 171, respectively.

A plurality of pixel electrodes 191 are disposed on the passivationlayer 180, a plurality of first contact assistants 81 are disposed onthe gate line end portions 129 of the gate lines 121 and the substrate110 surrounding the gate line end portions 129 of the gate lines 121 inthe first opening 181, and a plurality of second contact assistants 82are is disposed on the data line end portions 179 of the data lines 171and the substrate 110 surrounding the data line end portions 179 of thedata lines 171 in the second opening 182. The planar shapes of the firstand second contact assistants 81 and 82 are respectively the same asplanar shapes of the first and second openings. The pixel electrodes 191and the first and second contact assistants 81 and 82 may comprise atransparent conductive material, such as indium tin oxide (“ITO”),indium zinc oxide (“IZO”), or the like, or a reflective metal, such asaluminum, silver, chromium, an alloy thereof, or the like, or acombination comprising at least one of the foregoing materials.

The pixel electrodes 191 are physically and electrically connected tothe drain electrodes 175 through the contact holes 185, and receive datavoltages from the drain electrodes 175.

The first and second contact assistants 81 and 82 substantially coverthe gate line end portions 129 of the gate lines 121 and the data lineend portions 179 of the data lines 171 in the openings 181 and 182, andare electrically connected thereto. The first and second contactassistants 81 and 82 protect the gate line end portions 129 and the dataline end portions 179, and facilitate adhesion of the gate line endportions 129 and data line end portions 179 to an external device.

The pixel electrodes 191 overlap the previous gate lines 121, includinglongitudinal portions 125 and the transverse portion 126, via the gateinsulating layer 140 and the passivation layer 180 to form storagecapacitors, and the storage capacitors maintain the data voltagesapplied to the pixel electrodes 191 even after the thin film transistorsare turned off. Also, the drain electrode quadrangle end portions 177 ofthe drain electrodes 175 overlap the transverse portion 126 of theprevious gate line 121 via the gate insulating layer 140, thesemiconductor quadrangle expansion 157, and the ohmic contact quadrangleexpansion 167 to form an additional storage capacitor. Alternatively,the pixel electrodes 191, or the drain electrodes 175, may overlap anadditional storage electrode line (not shown) and transmit a commonvoltage (“Vcom”) in place of the previous gate line 121 to form thestorage capacitor.

The gate insulating layer 140 and a portion of the passivation layer 180under the pixel electrodes 191 makes it easier to form a storagecapacitor, and thus, an additional region for forming the storagecapacitor is not required, thereby reducing or effectively preventing adecrease of the aperture ratio.

Also, the gate insulating layer 140 and the portion of the passivationlayer 180 remaining under the pixel electrodes 191 contributes toreducing the step difference of the thin films, such as the pixelelectrodes 191. Accordingly, when an alignment layer (not shown) isdisposed on the pixel electrodes 191, incomplete rubbing around thesteps may be reduced or substantially prevented, and when using ballspacers (not shown), a non-uniform cell gap generated by a heightdifference between the spacers disposed on high portions of the pixelelectrodes 191 and the spacers disposed on low portions of the pixelelectrodes 191 may be reduced or substantially eliminated. Also, displaydeterioration, such as light leakage which may be occur where adirection of the liquid crystal molecules (not shown) in the liquidcrystal layer (not shown) disposed around steps of the pixel electrodes191 is not regulated, may be reduced or substantially eliminated suchthat a reduction of the aperture ratio may be reduced or substantiallyprevented.

Next a manufacturing method of the thin film transistor array panel ofFIG. 1 to FIG. 3B according to an exemplary embodiment is described withreference to FIG. 4A to FIG. 14B with FIG. 1 to FIG. 3B.

FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG.11A, FIG. 12A, FIG. 13A, and FIG. 14A are cross-sectional views showingan exemplary embodiment of intermediate parts of a manufacturing processof the thin film transistor array panel shown in FIG. 2 according to anexemplary embodiment taken along line IIIA-IIIA′, and FIG. 4B, FIG. 5B,FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B, FIG.13B, and FIG. 14B are cross-sectional views showing intermediate partsof a manufacturing process of the thin film transistor array panel shownin FIG. 2 according to an exemplary embodiment taken along linesIIIB-IIIB′ and IIIB′-IIIB″.

Referring to FIG. 4A and FIG. 4B, a metal having a low resistance, suchas a metal comprising aluminum (Al), a metal comprising silver (Ag), ametal comprising copper (Cu), or the like, or a combination comprisingat least one of the foregoing metals, is disposed on an insulatingsubstrate 110, which may comprise transparent glass, transparentplastic, or the like, or a combination comprising at least one of theforegoing transparent materials, and patterned by photolithography toform a plurality of gate lines 121 each of which includes gateelectrodes 124, longitudinal portions 125, a transverse portion 126, anda gate line end portion 129.

Referring to FIG. 5A and FIG. 5B, a gate insulating layer 140, which maycomprise silicon nitride, silicon oxide, or the like, or a combinationcomprising at least one of the foregoing materials, an intrinsicsemiconductor layer 150, which may comprise amorphous silicon,polysilicon, or the like, or a combination comprising at least one ofthe foregoing materials, an impurity-doped semiconductor layer 160, anda data conductive layer 170 are sequentially disposed on the substrate110 and the gate lines 121.

Next, referring to FIG. 6A and FIG. 6B, a photosensitive film (notshown) is disposed on the data conductive layer 170, exposed to lightusing a photo mask (not shown), and developed to form a photosensitivefilm pattern including a thick portion 52 and a thin portion 54.

In an embodiment, when the photosensitive film (not shown) has negativephotosensitivity, thus portions exposed to light remain, the photo mask(not shown) in the A region is transparent such that light istransmitted, the photo mask (not shown) in the C region is opaque suchthat light is blocked, and the photo mask (not shown) in the B region istranslucent such light is partially transmitted. The photosensitive filmcorresponding to the A region where light is transmitted forms the thickportion 52, the photosensitive film corresponding to the C region iscompletely removed, and the photosensitive film corresponding to the Bregion forms the thin portion 54. Alternatively, when the photosensitivefilm (not shown) has positive photosensitivity, thus the photosensitivefilm (not shown) exposed to light is removed, the transmittances of theA and C regions of the photo mask (not shown) are reversed and the Bregion is still translucent.

The photo mask (not shown) in the C region may include a pattern such asa slit, a lattice, or the like, or a combination comprising at least oneof the foregoing patterns, or may be a translucent film to control thetransmittance of light. The width of the slits or the intervals betweenlattice patterns may be less than the resolution of a light exposureused in the exposing process, and when a translucent film is used, thinfilms comprising an intermediate transmittance or an intermediatethickness may be used.

Next, referring to FIG. 7A and FIG. 7B, the data conductive layer 170,the impurity-doped semiconductor layer 160, and the intrinsicsemiconductor layer 150, which are disposed in the C region, are removedby a wet or a dry etching process using the thick and thinphotosensitive film patterns 52 and 54, respectively as an etching maskto form a plurality of data conductor layers 174, a plurality of ohmiccontact layers 164, and a plurality of semiconductor stripes (not shown)including semiconductor stripe protrusions 154 and a semiconductor endportions 159, each comprising substantially the same planar shape.

Next, referring to FIG. 8A and FIG. 8B, the thick and thinphotosensitive film patterns 52 and 54 are ashed using an oxidationplasma to reduce a thickness such that the thin photosensitive filmpattern 54 of the photosensitive film pattern disposed in the B regionis removed. In an embodiment, the thickness of the thick photosensitivefilm pattern 52 is also reduced by approximately the thickness of thethin photosensitive film pattern 54.

Next, as shown in FIG. 9A and FIG. 9B, the data conductor layer 174 andthe portion of the ohmic contact layer 164 corresponding to the B regionare removed using the remaining portion of the thick photosensitive filmpattern 52 to dispose a plurality of data lines 171 including sourceelectrodes 173 and a data line end portions 179, a plurality of drainelectrodes 175, including drain electrode quadrangle end portions 177, aplurality of ohmic contact stripes (not shown) including ohmic contactstripe protrusions 163 and an ohmic contact end portions 169, and aplurality of ohmic contact islands 165, including ohmic contactquadrangle end portions 167. In an embodiment, the data conductor layer174 may be wet-etched, and the ohmic contact layer 164 may bedry-etched.

Next, referring to FIG. 10A and FIG. 10B, the remaining portion of thethick photosensitive film pattern 52 is removed, and an inorganicmaterial or an organic material is disposed to form a passivation layer180.

Next, referring to FIG. 11A and FIG. 11B, a photosensitive film (notshown) is disposed on the passivation layer 180, and is exposed to lightusing a photo mask (not shown) and developed to form a photosensitivefilm pattern including a thick portion 56 and a thin portion 58.

When the photosensitive film (not shown) has negative photosensitivity,thus portions exposed to light remain, the photo mask (not shown) in theP region is transparent such that light is transmitted, the photo mask(not shown) in the R region is opaque such that light is blocked, andthe photo mask (not shown) in the Q region is translucent such thatlight is partially transmitted. The photosensitive film corresponding tothe P region, where light is transmitted, forms the thick portion 56,the photosensitive film corresponding to the R region is completelyremoved, and the photosensitive film corresponding to the Q region formsthe thin portion 58. Alternatively, when the photosensitive film (notshown) has positive photosensitivity, thus portions of thephotosensitive film (not shown) exposed to light are removed, a relativetransmittance of the P and R regions of the photo mask (not shown) arereversed and the Q region is still translucent.

Next, as shown in FIG. 12A and FIG. 12B, the passivation layer 180 andthe gate insulating layer 140, which are disposed in the R region, areremoved by a method such as dry etching, or the like, using the thickportion 56 and the thin portion 58 as an etching mask. In an embodiment,contact holes 185 exposing the drain electrode quadrangle end portions177 of the drain electrodes 175 and first and second openings 181 and182 exposing the gate line end portions 129 and the data line endportions 179 of the gate lines 121 and data lines 171, and the substrate110 surrounding the gate line end portions 129 and the data line endportions 179 are disposed. In an embodiment, an under-cut structure maybe formed under the thick portion 56 and the thin portion 58 in thecontact holes 185.

Next, referring to FIG. 13A and FIG. 13B, the thick portion 56 and thethin portion 58 are substantially entirely etched to reduce a thicknessthereof such that the thin portion 58 of the photosensitive film patterndisposed in the Q region is removed. Here, a thickness of the thickportion 56 is also reduced by a thickness of the thin portion 58.

Next, as shown in FIG. 14A and FIG. 14B, a conductive layer 190,comprising a transparent conductive material, such as ITO, IZO, or thelike, or a reflective metal, or a combination comprising at least one ofthe foregoing materials, is disposed and heated. In an embodiment, theheating temperature may be between about 100° C. to about 250° C.,specifically between about 140° C. to about 220° C., more specificallybetween about 150° C. to about 210° C. In an embodiment, various gasessuch as oxygen gas (O₂) are extracted from the remaining portion of thethick portion 56 such that the conductive layer 190 disposed in the Pregion, specifically the conductive layer 190 disposed on the remainingportion of the thick portion 56, is cracked and is lifted up. Thelifting off of the thick portion 56 is facilitated by the cracks in theconductive layer 190, and accordingly, the conductive layer 190 disposedon the thick portion 56 is removed together. As a result, as shown inFIG. 3A and FIG. 3B, pixel electrodes 191 and first and second contactassistants 81 and 82 are completed. Thus, in an embodiment, since thethick portion 56 is removed using cracks that are generated in theconductive layer 190 through a heating process, it is not necessary toform a big step difference in the conductive layer 190 or to remove thegate insulating layer 140 and the passivation layer 180 under theconductive layer 190. Also, disorder of the arrangement of the liquidcrystal molecules around the steps may be reduced.

According to an exemplary embodiment, a thin film transistor array panelmay be manufactured using three photolithographic processes, therebyreducing the manufacturing cost and time. Also, formation of a storagecapacitor can be easier because the gate insulating layer 140 and thepassivation layer 180 are left disposed between the pixel electrode 191and the substrate 110, which results in an increased aperture ratio.

While this invention has been described in conjunction with exemplaryembodiments, it is to be understood that the invention is not limited tothe disclosed embodiments, but, on the contrary, includes variousmodifications and equivalent arrangements included within the spirit andscope of this disclosure and the appended claims.

1. A thin film transistor array panel comprising: a substrate; a firstgate line disposed on the substrate and comprising a gate electrode; astorage electrode disposed in a layer which is the same layer as a layerof the first gate line; a gate insulating layer disposed on the firstgate line and the storage electrode; a semiconductor disposed on thegate insulating layer and comprising a channel portion; a data linedisposed on the semiconductor and comprising a source electrode; a drainelectrode disposed on the semiconductor and facing the source electrode;a passivation layer disposed on the gate insulating layer, the dataline, and the drain electrode, the passivation layer comprising acontact hole which exposes a portion of the drain electrode; and a pixelelectrode disposed on the passivation layer and electrically connectedto the drain electrode through the contact hole, wherein the gateinsulating layer and the passivation layer are interposed between thepixel electrode and the substrate except for a region corresponding tothe contact hole, and wherein the pixel electrode overlaps the storageelectrode via the gate insulating layer and the passivation layer. 2.The thin film transistor array panel of claim 1, wherein the storageelectrode comprises a portion of a second gate line, which is parallelto the first gate line, and transmits a gate signal.
 3. The thin filmtransistor array panel of claim 1, wherein the passivation layer furthercomprises a first opening, which exposes an end portion of the firstgate line, and a second opening, which exposes an end portion of thedata line, and wherein the thin film transistor array panel furthercomprises: a first contact assistant disposed in the first opening andelectrically connected to the end portion of the first gate line; and asecond contact assistant disposed in the second opening and electricallyconnected to the end portion of the data line.
 4. The thin filmtransistor array panel of claim 3, wherein the first contact assistantfurther contacts the substrate surrounding the end portion of the firstgate line, and the second contact assistant further contacts thesubstrate surrounding the end portion of the data line.
 5. The thin filmtransistor array panel of claim 1, wherein a planar shape of thesemiconductor, except for the channel portion, is the same as a planarshape of the data line and the drain electrode.
 6. The thin filmtransistor array panel of claim 5, wherein the storage electrodecomprises a portion of a second gate line, which is parallel to thefirst gate line and transmits a gate signal.
 7. The thin film transistorarray panel of claim 5, wherein the passivation layer further comprisesa first opening, which exposes an end portion of the first gate line,and a second opening, which exposes an end portion of the data line, andwherein the thin film transistor array panel further comprises: a firstcontact assistant disposed in the first opening and electricallyconnected to the end portion of the first gate line; and a secondcontact assistant disposed in the second opening and electricallyconnected to the end portion of the data line.
 8. The thin filmtransistor array panel of claim 7, wherein the first contact assistantfurther contacts the substrate surrounding the end portion of the firstgate line, and the second contact assistant further contacts thesubstrate surrounding the end portion of the data line.